1. Field of the Invention
The invention relates to a semiconductor device, and more particularly, to a method for patterning an active region in a semiconductor device using a space patterning process.
2. Brief Description of Related Technology
As the degree of integration of a semiconductor device increases and a design-rule is reduced, a fine pattern size is required. However, pattern size limits of optical exposure apparatuses required for forming the fine pattern make it difficult to reduce the design-rule. A maximum numeral aperture (NA) for conventional optical exposure machines is about 1.35. The limit of resolution is about 40 nm, based on a half pitch, when an ArF laser is used as a light source. As a result, it is difficult to implement a single exposure using a cell structure, such as 8F2 or 6F2 at a resolution of 40 nm or less. Thus, in order to form the fine pattern, a double patterning method is used. When using the double patterning method, an overlay of the pattern elements must be made zero such that the pattern elements are separate and distinct. However, t it is difficult to make the overlay of the pattern elements zero and make the size of the pattern elements constant.
FIG. 1 is a view showing the 8F2 cell structure of a general DRAM device. FIG. 2 is a view showing the 4F2 cell structure of the DRAM device. FIGS. 3a and 3b are views explaining problems caused when the 4F2 cell structure of FIG. 2 is formed in an actual pattern.
Referring to FIG. 1, a pattern 100 represents an active region, F2 represents a unit region of a cell storing 1 bit, and F represents one minimum pitch. An area of a unit structure including four capacitors can be represented by 8F2. As the design-rule is reduced, fidelity of the pattern 100 defining the active region is reduced. The finest pattern formable by a conventional, commercially available device is a simple line and space pattern of about 40 nm, using a resolution enhancement technique (RET). However, when the pattern shape is a two-dimensional shape as shown in FIG. 1, a limit of an allowable design is forced to be large. Since it is difficult to progress the fineness of the pattern using the conventional, commercially available device, a different type of cell design has been proposed.
FIG. 2 shows a proposed type of cell design, the 4F2 cell structure. A pattern 200 represents an active region. The cell area of the 4F2 cell structure can be theoretically reduced to half the cell area of the 8F2 cell structure. As shown in FIG. 3a, however, a pattern 300 shape implemented when the 4F2 cell structure is substantially formed on a wafer is represented by a circle. Even in this case, it is difficult to guarantee uniformity between patterns because of a defect of resolution. The current exposure apparatus cannot sufficiently transfer diffraction information by a mask pattern because an interval between the patterns is too narrow. Referring to FIGS. 3a and 3b, when the pattern is implemented on a wafer in a 50 nm-grade 4F2 structure, an irregular pattern bridge 305 can be formed as a result of contrast degradation. Therefore, a need exists for a method of forming the active area that can implement many memory cells within a small area and a pattern in a stable shape.